module mult (
    input clk,
    input rst,
    input en,
    input [7:0] x,
    input [7:0] y,
    output [15:0] res
);
  reg [6:0] b;
  reg [6:0] c;
  reg [7:0] a;
  reg [2:0] cr;

  always @(posedge clk or negedge rst) begin
    if (!rst) begin
      b  <= 7'b0;
      c  <= 7'b0;
      a  <= 8'b0;
      cr <= 3'b0;
    end else if (en) begin
      b  <= x[6:0];
      c  <= y[6:0];
      a  <= 8'b0;
      cr <= 3'b0;
    end else if (cr != 3'd7) begin
      b <= b;
      {a, c} <= c[0] ? ({{1'b0, a} + b, c} >> 1) : ({a, c} >> 1);
      cr <= cr + 1'b1;
    end else begin
      b  <= b;
      c  <= c;
      a  <= a;
      cr <= cr;
    end
  end

  assign res = {x[7] ^ y[7], a, c};

endmodule
